1. Field
This application relates generally to memory controllers, and more particularly, to memory controllers with skew control.
2. Related Art
Memory controllers are an important component in processing systems because memories are generally intentionally made to have relatively simple operating characteristics. This reduces the costs of the memories and avoids having to commit the memories to particular applications or to operating according to a particular processing scheme. Thus, the memory controllers provide much of necessary control for bringing data into a particular platform in a manner that is efficient both in terms of speed and utility for that platform. Speeds continue to increase, and it is not uncommon for the data to be received in 72 bits at a time. For example, an in-line memory module may have 9 different memories operating in parallel at 8 bits (one byte) each, whereas each byte of data is typically captured with a data strobe signal (which may be single-ended or differential) driven by the memory during reads. As a consequence, skew is an important issue because all 72 bits being accessed simultaneously and each byte of data must be captured with its corresponding data strobe signal. With that many different bits, it is difficult, if not impossible, for all of the data to arrive at the same time. Thus, one technique has been to provide a delay for each data bit and/or data strobe that is selectable based on experiments to test what delay is desirable to offset the skew. This method can be referred to as deskew. Although this type of deskew requires significant space on the memory controller, it has been found to be effective for the case where there is a single source for each bit, or where a single source may be trained and applied to other sources (i.e., other DIMM modules). Demand for more memory in many situations, has resulted in memory configurations in which a single bit received by the memory controller is selectively provided by more than one memory. For example, a dual in-line memory module (DIMM) may have ranks of memories in which one or the other rank provides the bits. This can be extended to four ranks or even more. This results in a different skew with respect to the data strobe for the same bit depending on which memory it came from. This skew differential has been tolerable, but with speeds increasing, an amount of skew differential that was passable in the past may not be now.
Thus there is a need for skew control that overcomes or improves upon one or more of the issues raised above.